1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having an electrode embedded in a trench in contact with an insulating film.
2. Description of the Background Art
A trench gate type power MISFET (metal insulator semiconductor field-effect transistor) (semiconductor device) having an electrode embedded in a trench through an insulating film is known in general, as disclosed in Japanese Patent Laying-Open No. 2005-57050, for example.
In the conventional power MISFET disclosed in the aforementioned Japanese Patent Laying-Open No. 2005-57050, a channel layer (base layer) is formed on a drain layer, while a source layer is formed on the channel layer. In this power MISFET, a gate electrode is formed in a trench so provided as to reach the drain layer through the source layer and the channel layer through a gate insulating film. In this power MISFET, further, the trench is so shallowly formed as to arrange the lower end of the gate electrode in the vicinity of the upper surface of the drain layer. Thus, gate capacitance can be reduced.
In the power MISFET disclosed in the aforementioned Japanese Patent Laying-Open No. 2005-57050, however, a depletion layer formed on a p-n junction between the drain layer and the channel layer extends downward beyond the lower end of the gate electrode arranged in the vicinity of the upper surface of the drain layer, to disadvantageously increase ON-state resistance.